/*
 * @[H]:  Copyright (c) 2021 Phytium Information Technology, Inc. 
 * 
 *  SPDX-License-Identifier: Apache-2.0. 
 * 
 * @Date: 2021-08-13 08:26:30
 * @LastEditTime: 2021-08-23 16:55:03
 * @Description:  Description of file
 * @Modify History: 
 * * * Ver   Who        Date         Changes
 * * ----- ------     --------    --------------------------------------
 */

#ifndef DRIVERS_FGDMA_HW_H
#define DRIVERS_FGDMA_HW_H

#ifdef __cplusplus
extern "C"
{
#endif

#include "fgdma.h"
#include "parameters.h"
#include "ft_io.h"
#include "ft_types.h"
#include "kernel.h"

    /* Global universal register */
#define FGDMA_GLOBAL_CTL_OFFSET 0
#define FGDMA_GLOBAL_INTR_STATE_OFFSET 0x4
#define FGDMA_GLOBAL_INTR_CTRL_OFFSET 0x8
#define FGDMA_GLOBAL_CHANNEL_LOW_POWER_CONTROL_OFFSET 0xc
#define FGDMA_GLOBAL_CHANNEL_QOS_CFG_OFFSET 0x10

    /* Chx  register*/
#define FGDMA_CHX_CTL_OFFSET 0
#define FGDMA_CHX_MODE_OFFSET 0x4
#define FGDMA_CHX_INT_CTRL_OFFSET 0x8
#define FGDMA_CHX_INT_STATE_OFFSET 0xC
#define FGDMA_CHX_LVI_OFFSET 0x10
#define FGDMA_CHX_TS_OFFSET 0x14
#define FGDMA_CHX_UPSADDR_OFFSET 0x18
#define FGDMA_CHX_LWSADDR_OFFSET 0x1C
#define FGDMA_CHX_UPDADDR_OFFSET 0x20
#define FGDMA_CHX_LWDADDR_OFFSET 0x24
#define FGDMA_CHX_XFER_CFG_OFFSET 0x28
#define FGDMA_CHX_LCP_OFFSET 0x2C
#define FGDMA_CHX_SECCTL_OFFSET 0x30
#define FGDMA_CHX_AW_CFG_OFFSET 0x3C
#define FGDMA_CHX_AR_CFG_OFFSET 0x40

    /* FGDMA_GLOBAL_CTL_OFFSET */
#define FGDMA_GLOBAL_CTL_OT_MASK GENMASK(11, 8)        //dma 传输outstanding 控制，实际数量为该寄存器值+1
#define FGDMA_GLOBAL_CTL_RD_ARB_MASK GENMASK(5, 5)     //dma 读请求仲裁模式: 0：轮询模式，1：采用Qos判断模式
#define FGDMA_GLOBAL_CTL_WR_ARB_MASK GENMASK(4, 4)     //dma 写请求仲裁模式: 0：轮询模式，1：采用Qos判断模式
#define FGDMA_GLOBAL_CTL_SOFT_RESET_MASK GENMASK(1, 1) //dma 软件复位信号，1表示进行复位，写0退出
#define FGDMA_GLOBAL_CTL_ENABLE_MASK GENMASK(0, 0)     //dma 使能信号，1表示使能，写0表示disable

    /* FGDMA_GLOBAL_INTR_STATE_OFFSET */
#define FGDMA_GLOBAL_CTRL_CHANNEL0_INTR_STATE_MASK GENMASK(0, 0)
#define FGDMA_GLOBAL_CTRL_CHANNEL1_INTR_STATE_MASK GENMASK(1, 1)
#define FGDMA_GLOBAL_CTRL_CHANNEL2_INTR_STATE_MASK GENMASK(2, 2)
#define FGDMA_GLOBAL_CTRL_CHANNEL3_INTR_STATE_MASK GENMASK(3, 3)
#define FGDMA_GLOBAL_CTRL_CHANNEL4_INTR_STATE_MASK GENMASK(4, 4)
#define FGDMA_GLOBAL_CTRL_CHANNEL5_INTR_STATE_MASK GENMASK(5, 5)
#define FGDMA_GLOBAL_CTRL_CHANNEL6_INTR_STATE_MASK GENMASK(6, 6)
#define FGDMA_GLOBAL_CTRL_CHANNEL7_INTR_STATE_MASK GENMASK(7, 7)
#define FGDMA_GLOBAL_CTRL_CHANNEL8_INTR_STATE_MASK GENMASK(8, 8)
#define FGDMA_GLOBAL_CTRL_CHANNEL9_INTR_STATE_MASK GENMASK(9, 9)
#define FGDMA_GLOBAL_CTRL_CHANNEL10_INTR_STATE_MASK GENMASK(10, 10)
#define FGDMA_GLOBAL_CTRL_CHANNEL11_INTR_STATE_MASK GENMASK(11, 11)
#define FGDMA_GLOBAL_CTRL_CHANNEL12_INTR_STATE_MASK GENMASK(12, 12)
#define FGDMA_GLOBAL_CTRL_CHANNEL13_INTR_STATE_MASK GENMASK(13, 13)
#define FGDMA_GLOBAL_CTRL_CHANNEL14_INTR_STATE_MASK GENMASK(14, 14)
#define FGDMA_GLOBAL_CTRL_CHANNEL15_INTR_STATE_MASK GENMASK(15, 15)
#define FGDMA_GLOBAL_CTRL_CHANNEL15_INTR_STATE_MASK GENMASK(15, 15)

    /* FGDMA_GLOBAL_INTR_CTRL_OFFSET */
#define FGDMA_GLOBAL_CTRL_CHANNEL0_INTR_CTRL_MASK GENMASK(0, 0)
#define FGDMA_GLOBAL_CTRL_CHANNEL1_INTR_CTRL_MASK GENMASK(1, 1)
#define FGDMA_GLOBAL_CTRL_CHANNEL2_INTR_CTRL_MASK GENMASK(2, 2)
#define FGDMA_GLOBAL_CTRL_CHANNEL3_INTR_CTRL_MASK GENMASK(3, 3)
#define FGDMA_GLOBAL_CTRL_CHANNEL4_INTR_CTRL_MASK GENMASK(4, 4)
#define FGDMA_GLOBAL_CTRL_CHANNEL5_INTR_CTRL_MASK GENMASK(5, 5)
#define FGDMA_GLOBAL_CTRL_CHANNEL6_INTR_CTRL_MASK GENMASK(6, 6)
#define FGDMA_GLOBAL_CTRL_CHANNEL7_INTR_CTRL_MASK GENMASK(7, 7)
#define FGDMA_GLOBAL_CTRL_CHANNEL8_INTR_CTRL_MASK GENMASK(8, 8)
#define FGDMA_GLOBAL_CTRL_CHANNEL9_INTR_CTRL_MASK GENMASK(9, 9)
#define FGDMA_GLOBAL_CTRL_CHANNEL10_INTR_CTRL_MASK GENMASK(10, 10)
#define FGDMA_GLOBAL_CTRL_CHANNEL11_INTR_CTRL_MASK GENMASK(11, 11)
#define FGDMA_GLOBAL_CTRL_CHANNEL12_INTR_CTRL_MASK GENMASK(12, 12)
#define FGDMA_GLOBAL_CTRL_CHANNEL13_INTR_CTRL_MASK GENMASK(13, 13)
#define FGDMA_GLOBAL_CTRL_CHANNEL14_INTR_CTRL_MASK GENMASK(14, 14)
#define FGDMA_GLOBAL_CTRL_CHANNEL15_INTR_CTRL_MASK GENMASK(15, 15)
#define FGDMA_GLOBAL_CTRL_GLOBAL_INTR_ENABLE_MASK GENMASK(31, 31)

/* FGDMA_GLOBAL_CHANNEL_LOW_POWER_CONTROL_OFFSET   */
#define FGDMA_GLOBAL_CTRL_CHANNEL0_LPC_MASK GENMASK(0, 0) // 每一位对应一个通道时钟开启与关断，1 表示关断，0默认开启
#define FGDMA_GLOBAL_CTRL_CHANNEL1_LPC_MASK GENMASK(1, 1)
#define FGDMA_GLOBAL_CTRL_CHANNEL2_LPC_MASK GENMASK(2, 2)
#define FGDMA_GLOBAL_CTRL_CHANNEL3_LPC_MASK GENMASK(3, 3)
#define FGDMA_GLOBAL_CTRL_CHANNEL4_LPC_MASK GENMASK(4, 4)
#define FGDMA_GLOBAL_CTRL_CHANNEL5_LPC_MASK GENMASK(5, 5)
#define FGDMA_GLOBAL_CTRL_CHANNEL6_LPC_MASK GENMASK(6, 6)
#define FGDMA_GLOBAL_CTRL_CHANNEL7_LPC_MASK GENMASK(7, 7)
#define FGDMA_GLOBAL_CTRL_CHANNEL8_LPC_MASK GENMASK(8, 8)
#define FGDMA_GLOBAL_CTRL_CHANNEL9_LPC_MASK GENMASK(9, 9)
#define FGDMA_GLOBAL_CTRL_CHANNEL10_LPC_MASK GENMASK(10, 10)
#define FGDMA_GLOBAL_CTRL_CHANNEL11_LPC_MASK GENMASK(11, 11)
#define FGDMA_GLOBAL_CTRL_CHANNEL12_LPC_MASK GENMASK(12, 12)
#define FGDMA_GLOBAL_CTRL_CHANNEL13_LPC_MASK GENMASK(13, 13)
#define FGDMA_GLOBAL_CTRL_CHANNEL14_LPC_MASK GENMASK(14, 14)
#define FGDMA_GLOBAL_CTRL_CHANNEL15_LPC_MASK GENMASK(15, 15)

    /* FGDMA_GLOBAL_CHANNEL_QOS_CFG_OFFSET */
#define FGDMA_GLOBAL_CHANNEL_QOS_CFG_ARGOS_MASK GENMASK(7, 4)
#define FGDMA_GLOBAL_CHANNEL_QOS_CFG_AWQOS_MASK GENMASK(3, 0)

    /* FGDMA_CHX_CTL_OFFSET */
#define FGDMA_CHX_CTL_SOFT_RESET_MASK GENMASK(4, 4)
#define FGDMA_CHX_CTL_ENABLE_MASK GENMASK(0, 0)

    /* FGDMA_CHX_MODE_OFFSET */
#define FGDMA_CHX_MODE_RD_QOS_MASK GENMASK(23, 20) /* CHX 读请求Qos 配置 */
#define FGDMA_CHX_MODE_RD_QOS_ENABLE_MASK GENMASK(16, 16)
#define FGDMA_CHX_MODE_WR_QOS_MASK GENMASK(15, 12) /* CHX  写请求Qos 配置 */
#define FGDMA_CHX_MODE_WR_QOS_ENABLE_MASK GENMASK(8, 8)
#define FGDMA_CHX_MODE_BDL_ROLL_ENABLE_MASK GENMASK(4, 4) /* 是否用CHX qos cfg 中的值替换该读请求的Qos ：1 表示替换 ，0 不替换 */
#define FGDMA_CHX_MODE_MODE_ENABLE_MASK GENMASK(0, 0)     /* 配置当前采用direct 或者BDL 链表模式 。1 采用Direct 模式 0 采用BDL 模式 */

    /* FGDMA_CHX_INT_CTRL_OFFSET */
#define FGDMA_CHX_INT_CTRL_TRANS_END_ENABLE_MASK GENMASK(3, 3)  /* CHX 所以数据传输完成中断输出控制，1表示允许输出，0表示不允许 */
#define FGDMA_CHX_INT_CTRL_BDL_END_ENABLE_MASK GENMASK(2, 2)    /* CHX bdl 条目数据传输完成中断输出控制，1表示允许输出，0表示不允许  */
#define FGDMA_CHX_INT_CTRL_FIFO_FULL_ENABLE_MASK GENMASK(1, 1)  /* CHX ARM满中断 1表示允许输出，0表示不允许 */
#define FGDMA_CHX_INT_CTRL_FIFO_EMPTY_ENABLE_MASK GENMASK(0, 0) /* CHX ARM空中断 1表示允许输出，0表示不允许 */

    /* FGDMA_CHX_INT_STATE_OFFSET */
#define FGDMA_CHX_INT_STATE_BUSY_MASK GENMASK(4, 4)       /* CHX 处于数据传输中，写1 清0 */
#define FGDMA_CHX_INT_STATE_TRANS_END_MASK GENMASK(3, 3)  /* CHX 处于传输完成状态，direct 模式时，表示所有数据传输完成，BDL 模式表示当前所有BDL条目传输完成： 写1清0 */
#define FGDMA_CHX_INT_STATE_BDL_END_MASK GENMASK(2, 2)    /* CHX 在BDL模式下，表示当前一个BDL 条目数据传输完成；Direct 模式下该位始终为0 ，  写1清0 */
#define FGDMA_CHX_INT_STATE_FIFO_FULL_MASK GENMASK(1, 1)  /* CHX FIFO 满状态，写1清0 */
#define FGDMA_CHX_INT_STATE_FIFO_EMPTY_MASK GENMASK(0, 0) /* CHX FIFO 空状态，写1清0 */
#define FGDMA_CHX_INT_STATE_ALL_MASK GENMASK(4, 0)

    /* FGDMA_CHX_LVI_OFFSET */
#define FGDMA_CHX_LVi_MASK GENMASK(31, 0) /* CHX last vaild index,即链表末模式下BDL有效条目，实际有效条目=该寄存器值+1 */

    /* FGDMA_CHX_TS_OFFSET */
#define FGDMA_CHX_TS_MASK GENMASK(31, 0) /* CHX 在direct 模式下操作的的总Byte数量 */

    /* FGDMA_CHX_UPSADDR_OFFSET */
#define FGDMA_CHX_UPSADDR_MASK GENMASK(31, 0) /* CHX 源地址高32bits */

    /* FGDMA_CHX_LWSADDR_OFFSET */
#define FGDMA_CHX_LWSADDR_MASK GENMASK(31, 0) /* CHX 源地址低32bits */

    /* FGDMA_CHX_UPDADDR_OFFSET */
#define FGDMA_CHX_UPDADDR_MASK GENMASK(31, 0) /* CHX 目标地址高32bits */

    /* FGDMA_CHX_LWDADDR_OFFSET */
#define FGDMA_CHX_LWDADDR_MASK GENMASK(31, 0) /* CHX 目标地址低32bits */

    /* FGDMA_CHX_XFER_CFG_OFFSET */
#define FGDMA_CHX_XFER_CFG_AR_BRUST_LENGTH_MASK GENMASK(31, 24) /* CHX 读请求Burst length 大小 */
#define FGDMA_CHX_XFER_CFG_AR_SIZE_MASK GENMASK(22, 20)         /* CHX 读请求Size 大小 ， 支持 1、2、8、16 Byte */
#define FGDMA_CHX_XFER_CFG_ARB_BRUST_MASK GENMASK(17, 16)       /* CHX 读请求Brust 类型： 0：fix ，1：incr */
#define FGDMA_CHX_XFER_CFG_AW_BRUST_LENGTH_MASK GENMASK(31, 24) /* CHX 写请求Burst length 大小 */
#define FGDMA_CHX_XFER_CFG_AW_SIZE_MASK GENMASK(22, 20)         /* CHX 写请求Size 大小 ， 支持 1、2、8、16 Byte */
#define FGDMA_CHX_XFER_CFG_AWB_BRUST_MASK GENMASK(17, 16)       /* CHX 写请求Brust 类型： 0：fix ，1：incr */

    /* FGDMA_CHX_LCP_OFFSET */
#define FGDMA_CHX_LCP_MASK GENMASK(31, 0)

    /* FGDMA_CHX_SECCTL_OFFSET */
#define FGDMA_CHX_SECCTL_MASK GENMASK(31, 0) /* CHX 安全控制寄存器，仅安全状态可访问 */

    /* FGDMA_CHX_AW_CFG */
#define FGDMA_CHX_AW_CFG_AWCACHE_MASK GENMASK(3, 0)  /* CHX dma awcache */
#define FGDMA_CHX_AW_CFG_AWREGION_MASK GENMASK(7, 4) /* CHX dma awregion */
#define FGDMA_CHX_AW_CFG_AWPROT_MASK GENMASK(9, 8)
#define FGDMA_CHX_AW_CFG_AWDOMAIN_MASK GENMASK(13, 12) /* chx awdomain */
#define FGDMA_CHX_AW_CFG_AWSNOOP_MASK GENMASK(18, 16)
#define FGDMA_CHX_AW_CFG_AWBAR_MASK GENMASK(21, 20)

/* FGDMA_CHX_AR_CFG_OFFSET */
#define FGDMA_CHX_AR_CFG_AWCACHE_MASK GENMASK(3, 0)  /* CHX dma arcache */
#define FGDMA_CHX_AR_CFG_AWREGION_MASK GENMASK(7, 4) /* CHX dma arregion */
#define FGDMA_CHX_AR_CFG_AWPROT_MASK GENMASK(9, 8)
#define FGDMA_CHX_AR_CFG_AWDOMAIN_MASK GENMASK(13, 12) /* chx ardomain */
#define FGDMA_CHX_AR_CFG_AWSNOOP_MASK GENMASK(18, 16)
#define FGDMA_CHX_AR_CFG_AWBAR_MASK GENMASK(21, 20)

/**
*
* This macro reads the given register.
*
* @param    base_addr is the base address of the device.
* @param    reg_offset is the register offset to be read.
*
* @return   The 32-bit value of the register
*
* @note     None.
*
*****************************************************************************/
#define FGDMA_READREG(base_addr, reg_offset) \
    FtIn32((base_addr) + (u32)(reg_offset))

/****************************************************************************/
/**
*
* This macro writes the given register.
*
* @param    base_addr is the base address of the device.
* @param    reg_offset is the register offset to be written.
* @param    data is the 32-bit value to write to the register.
*
* @return   None.
*
* @note     None.
*
*****************************************************************************/
#define FGDMA_WRITEREG(base_addr, reg_offset, data) \
    FtOut32((base_addr) + (u32)(reg_offset), (u32)(data))

#define FGDMA_SETBIT(base_addr, reg_offset, data) \
    FtSetBit32((base_addr) + (u32)(reg_offset), (u32)(data))

#define FGDMA_CLEARBIT(base_addr, reg_offset, data) \
    FtClearBit32((base_addr) + (u32)(reg_offset), (u32)(data))

    void FGdmaHwInit(FGdma *instance_p);

#ifdef __cplusplus
}
#endif

#endif // !
